Scheduling tasks in a communications network

Abstract

A time trigger for instruction execution can be contained within the instruction itself. A time stamp value associated with each of a sequence of instructions, which are written into a FIFO memory (9) by an application specific controller (1), is compared with the output value of a counter (11). When the two values are equal, a comparator 10 sends a command to an instruction decoder (8) to execute the current instruction. The invention has the advantage of a reduced interrupt overhead and his particular application to HiperLAN 2 systems in which it can be incorporated without affecting the protocol handling.

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Patent Citations (2)

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Cited By (2)

    Publication numberPublication dateAssigneeTitle
    US-7594097-B2September 22, 2009Imagination Technologies LimitedMicroprocessor output ports and control of instructions provided therefrom
    WO-2006005964-A1January 19, 2006Imagination Technologies LimitedPorts de sortie de microprocesseur et commande d'instructions fournie par ces ports